High Performance Computing and Computer Architecture<\/strong><\/p>\n

\n
• On-chip nanophotonic solutions for processors and high-performance systems<\/li>\n
• Innovative parallel processors and memory hierarchy architectures<\/li>\n
• Novel caching schemes for multi-core processors<\/li>\n
• Exploitation of advanced processor features with C++<\/li>\n<\/ul>\n

  Productivity in programming<\/strong><\/p>\n

  \n
  • Efficient programming techniques and tools for cross-platform development for GPGPU and multi-\/many-core (NVidia, ATI, Phi, FPGA) with OpenCL and with our patented approach<\/li>\n
  • IDE-level tools and techniques for increased productivity and correctness in programming<\/li>\n
  • Development of a high-level C++(11\/14\/17) library for numeric computations<\/li>\n
  • Optimized compilation for large codebases<\/li>\n<\/ul>\n

    High-performance data-elaboration<\/strong><\/p>\n

    \n
    • Elaboration of astronomical images – big and with temporal constraints – for identifying space debris and space objects that could hit the earth or artificial satellites<\/li>\n
    • Effective processing of streaming big-data (e.g. CERN LHC)<\/li>\n
    • Analysis and optimization of block-chain and crypto-currency software for GPUs and CPUs<\/li>\n<\/ul>\n

      Innovative systems\/services and mobile platforms<\/strong><\/p>\n

      \n
      • Task planning in complex industrial environments<\/li>\n
      • Simulation of heterogeneous hybrid vehicles in a 3D environment<\/li>\n
      • Augmented virtuality framework for holistic management of geographic spatial-temporal, social data<\/li>\n<\/ul>\n

        \u00a0<\/strong>Cybersecurity<\/strong><\/p>\n

        \n
        • Architectural countermeasures to security threats in cyber-physical systems (e.g. autonomous vehicles and systems)<\/li>\n
        • Analysis and implementation of block-chain algorithms on mobile devices<\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"

          High Performance Computing and Computer Architecture On-chip nanophotonic solutions for processors and high-performance systems Innovative parallel processors and memory hierarchy architectures Novel caching schemes for multi-core processors Exploitation of advanced processor features with C++ Productivity in programming Efficient programming techniques Continue reading Thesis topics<\/span>→<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":99,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0},"_links":{"self":[{"href":"http:\/\/frankie.dii.unisi.it\/sandroHome\/index.php\/wp-json\/wp\/v2\/pages\/107"}],"collection":[{"href":"http:\/\/frankie.dii.unisi.it\/sandroHome\/index.php\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"http:\/\/frankie.dii.unisi.it\/sandroHome\/index.php\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"http:\/\/frankie.dii.unisi.it\/sandroHome\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/frankie.dii.unisi.it\/sandroHome\/index.php\/wp-json\/wp\/v2\/comments?post=107"}],"version-history":[{"count":2,"href":"http:\/\/frankie.dii.unisi.it\/sandroHome\/index.php\/wp-json\/wp\/v2\/pages\/107\/revisions"}],"predecessor-version":[{"id":136,"href":"http:\/\/frankie.dii.unisi.it\/sandroHome\/index.php\/wp-json\/wp\/v2\/pages\/107\/revisions\/136"}],"up":[{"embeddable":true,"href":"http:\/\/frankie.dii.unisi.it\/sandroHome\/index.php\/wp-json\/wp\/v2\/pages\/99"}],"wp:attachment":[{"href":"http:\/\/frankie.dii.unisi.it\/sandroHome\/index.php\/wp-json\/wp\/v2\/media?parent=107"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}